1. Technical Field
The present disclosure relates to high density memory devices, and particularly to memory devices in which multiple planes of memory cells are arranged to provide a three-dimensional 3D array.
2. Description of Related Art
As critical dimensions of devices in integrated circuits shrink to the limits of common memory cell technologies, designers have been looking to techniques for stacking multiple planes of memory cells to achieve greater storage capacity, and to achieve lower costs per bit.
FIG. 1 is a perspective illustration of an implementation of a three-dimensional (3D) integrated circuit device using a vertical gate structure. The device 100 illustrated in FIG. 1 includes a plurality of stacks of conductive strips alternating with insulating strips in the Z-direction on an integrated circuit substrate.
In the example shown in FIG. 1, a multilayer array is formed on an insulating layer, and includes a plurality of structures of a conductive material, such as a plurality of word lines 125-1 WL through 125-N WL, arranged orthogonally over and conformal with the plurality of stacks. Conductive strips in the stacks of conductive strips in multiple planes (e.g. 112, 113, 114, and 115) can include channels for the memory elements, and structures in the plurality of structures (e.g. 125-1 WL through 125-N WL) can be arranged as word lines and string select lines including vertical gates for memory elements. Conductive strips in the same plane are electrically coupled together by a stack of linking elements (e.g. 102B, 103B, 104B and 105B).
A contact structure including a stack of linking elements 112A, 113A, 114A, and 115A terminate conductive strips, such as the conductive strips 112, 113, 114, and 115 in the plurality of stacks. As illustrated, these linking elements 112A, 113A, 114A, and 115A are electrically connected to different bit lines for connection to decoding circuitry to select planes within the array. These linking elements 112A, 113A, 114A, and 115A can be patterned at the same time that the plurality of stacks is defined.
The stack of linking elements (e.g. 102B, 103B, 104B and 105B) are separated by insulating layers (not shown) in the Z-direction, and terminate conductive strips, such as conductive strips 102, 103, 104, and 105. The insulating layers can include the insulating material as described for the insulating strips between the conductive strips in the Z-direction. A plurality of interlayer connectors (e.g. 172, 173, 174, and 175) in the stack of linking elements (e.g. 102B, 103B, 104B, and 105B) extend from a connector surface to respective linking elements. Patterned conductor lines on top of the connector surface can be connected to respective interlayer connectors. As illustrated, interlayer connectors 172, 173, 174, 175 electrically connect linking elements 102B, 103B, 104B, and 105B to different bit lines in patterned conductor lines, such as a metal layer ML3, for connection to decoding circuitry to select planes within the array. The stack of linking elements 102B, 103B, 104B, and 105B can be patterned at the same time that the plurality of stacks is defined.
Any given stack of conductive strips is coupled to either the stack of linking elements 112A, 113A, 114A, and 115A, or the stack of linking elements 102B, 103B, 104B, and 105B, but not both. The stack of conductive strips 112, 113, 114, and 115 is terminated at one end by the stack of linking elements 112A, 113A, 114A, and 115A, passes through SSL gate structure 119, ground select line GSL 126, word lines 125-1 WL through 125-N WL, ground select line GSL 127, and is terminated at the other end by source line 128. The stack of conductive strips 112, 113, 114, and 115 does not reach the stack of linking elements 102B, 103B, 104B, and 105B.
The stack of conductive strips 102, 103, 104, and 105 is terminated at one end by the stack of linking elements 102B, 103B, 104B, and 105B, passes through SSL gate structure 109, ground select line GSL 127, word lines 125-N WL through 125-1 WL, ground select line GSL 126, and is terminated at the other end by a source line (obscured by other parts of the figure). The stack of conductive strips 102, 103, 104, and 105 does not reach the stack of linking elements 112A, 113A, 114A, and 115A.
A memory layer is disposed in interface regions at cross-points between surfaces of the conductive strips 112-115 and 102-105 in the plurality of stacks of conductive strips, and the plurality of structures of a conductive material, such as a plurality of word lines 125-1 WL through 125-N WL. In particular, the memory layer is formed on side surfaces of the conductive strips in the plurality of stacks. Memory elements are disposed in interface regions at cross-points between side surfaces of the plurality of stacks and the plurality of word lines. Ground select lines GSL 126 and GSL 127 are conformal with the plurality of stacks, similar to the word lines.
Every stack of conductive strips is terminated at one end by linking elements and at the other end by a source line. For example, the stack of conductive strips 112, 113, 114, and 115 is terminated at one end by linking elements 112A, 113A, 114A, and 115A, and terminated on the other end by a source line 128. At the near end of the figure, every other stack of conductive strips is terminated by the linking elements 102B, 103B, 104B, and 105B, and every other stack of conductive strips is terminated by a separate source line. At the far end of the figure, every other stack of conductive strips is terminated by the linking elements 112A, 113A, 114A, and 115A, and every other stack of conductive strips is terminated by a separate source line.
Bit lines and string select gate structures are formed at the metals layers ML1, ML2, and ML3. Bit lines are coupled to a plane decoder (not shown). String select gate structures are coupled to a string select line decoder (not shown).
The ground select lines GSL 126 and 127 can be patterned during the same step that the word lines 125-1 WL through 125-N WL are defined. Ground select devices are formed at cross-points between surfaces of the plurality of stacks and ground select lines GSL 126 and 127. The SSL gate structures 119 and 109 can be patterned during the same step in which the word lines 125-1 WL through 125-N WL are defined. String select devices are formed at cross-points between surfaces of the plurality of stacks and string select (SSL) gate structures 119 and 109. These devices are coupled to decoding circuitry for selecting the strings within particular stacks in the array.
In the memory device of FIG. 1, the trenches separating adjacent stacks of conductive strips have the same width. Narrowing the distance between adjacent stacks of conductive strips could increase the memory density. However, further narrowing the distance between adjacent stacks of conductive strips increases the difficulty of forming quality memory materials for both stacks, as well as gate material. It would be desirable to increase the memory density of the memory device by narrowing trenches between adjacent stacks of conductive strips, without compromising the quality of the memory material and gate material which is formed inside the trenches.